Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeB

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Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for Lte Enodeb

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Buy now Loading Easy Return Policy. Help Center Got a question? Yet we believe that it is possible to devise a language that could appeal to most hardware and software engineers, and provide a suitable replacement of HDLs, while not being necessarily tied to the development of hardware components. We show such a language in this paper. We examine related work in section VI before concluding this article.

This model is a special case of Kahn Process Networks KPN [6], which is traditionally used as a model for threaded programs. A program behaving according to the KPN model is composed of a set of concurrent processes that send each other atomic data objects called tokens via unbounded unidirectional FIFOs through ports. Each process is composed of a sequence of reads, computations, and writes freely interleaved.

Conversely, in the DPN model, a process is called an actor and is composed of a sequence of firing rules defined below. A firing rule defines a non-preemptive uninterruptible quantum of computation as 1 the number of tokens that are consumed and produced, 2 a predicate that returns true if the rule can be satisfied, and 3 a function that produces output tokens from input tokens. A program that respects the DPN model executes by executing all its actors repeatedly. Each time an actor is executed, the first firing rule that can be satisfied is executed. Additionally, a firing rule can change the current state when it is executed.

Process networks have two properties that make them interesting for the description of hardware designs and multiprocessing software.

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They provide explicit concurrency, and also prohibit side-effects, in other words a process cannot modify the state variables of another process, as this would make the model non-deterministic [6]. The literature contains many articles on hardware synthesis and software code generation from both KPN e.

We use DPN rather than KPN because an actor can be mapped to hardware in a straightforward and predictable manner by executing each firing rule in a clock cycle [11]. It is also possible to analyze the behavior of DPN actors at compile-time [14], [15], which is useful to prevent deadlocks, or to reduce memory consumption [16]. This IR is described in [17] and is being used in an open-source compiler for dataflow programs called Orcc. It also has two procedures which can be in SSA form [18] , one that defines the predicate associated with the rule, and a second one that defines the behavior of the rule.

This allows the generation of higher-level and more readable source code, being C [12], VHDL [11], or other languages see the Orcc project for additional code generators. As presented in the previous section, a Dataflow Process Network is composed of a set of concurrent processes connected together via FIFO channels. A header is similar to a VHDL package or an include file in C or Verilog, and contains definitions of types, constants and stateless functions.

All these elements are internal to the task and cannot be accessed from other tasks or headers. This enforces the properties of the DPN model by allowing tasks to communicate only through ports. Conversely, such a relation is irrelevant when targeting software: what matters is that a task as a whole should minimize its Communication to Computation Ratio CCR to maximize its performance see [21] for a detailed study. Since the language can target hardware or software, it should be able to allow both use cases.

This requirement, as well as fifty years of programming, suggests that a sequential process is more appropriate than a list of firing rules for the description of a task.

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The first rule defines the consumption of tokens: in a cycle, data can be consumed from a given input port at most once, and it may be peeked or tested any number of times; we detail this with the semantics of conditional and loop statements. The second rule of the language defines the production of tokens: in a cycle, an output port can be written to at most once. The third rule is that an expression or a statement is executed in the current cycle, unless one of these rules cannot be verified, in which case execution continues in a new cycle.

The main function always starts a new cycle. The corresponding FSM is shown on Fig. Conditional and loop statements may be executed in the current cycle provided that they do not contain reads or writes: this kind of conditional or loop is purely computational. Otherwise, they become multi-cycle statements associated with additional states and transitions following the patterns shown on Fig. The read calls that appear in these conditions peek at the token present on the port without consuming it.

Hardware code generation or hardware synthesis of dataflow programs is not new. The work we present in this section is based on our previous work [11], which proposed an alternative to the existing approach of hardware synthesis of dataflow programs pioneered by Janneck et al.

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With the exception of artificial programs used to study properties of the model, this set covers all practical programs. DPN allows firing rules with an arbitrary number of tokens on input ports, which requires specific transformations and internal buffers for execution on hardware [22], which translates to an important overhead in terms of area. Previous work generated asynchronous handshake-style interfaces connected with FIFOs whose default length is one [10], [11].

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This has the advantage that different actors need not have the same execution rate, and that data is never lost because an actor is only executed if the FIFOs connected to its output ports are not full. We are taking a different approach from previous work: the generated hardware has no handshake signals, and no FIFOs. In the case of actors with different execution rates, this is only a problem if an actor produces more data than the actor it is connected to can consume, as it will overwrite unconsumed data.

To detect that, we use a cycle-accurate, instrumented, software simulation based on our previous work [17] , that detects overwrites. A network of tasks becomes a module that instantiates and connects the tasks together. Unless FIFOs are explicitly instantiated by the designer, this results in a strict one-to-one mapping between the DPN model and the generated hardware design. The second process is synchronous, and implements the behavior of each firing rule, executing at most one firing rule per clock cycle, reading data, performing operations, and writing data.

The RTL code is well structured, as opposed to the gate-level code often produced by HLS tools, and it respects a synthesis-friendly coding style. The MAC encapsulation converts a stream of bytes to Ethernet frames, by adding the preamble pattern and Start Frame Delimiter before the frame, and the CRC computed on-the-fly at the end of the frame. The speed is auto-negotiated and returned by the PHY configuration layer described below.

The design, with no optimization whatsoever, can run at a maximum frequency of Figure 7 presents the distribution of the area among the different networks. HLS reduces design time compared to traditional HDLs by raising the level of abstraction, but the C language [20] has many features that make no sense for hardware descriptions or cannot be transformed to synthesizable hardware such as sequence points, memory allocation, arbitrary pointers, system calls , while lacking features that are useful or necessary for hardware descriptions e.

A different type of approach is the use of a specific language whose semantics are either closer to hardware or even dedicated to hardware. BSV is based on the notion of atomic transactions whose semantics is close to firings. We gave an overview of its syntax, a subset of C with the addition of dataflow-specific constructs, and its semantics, which is based on the DPN model. We have several directions for future work. We are also examining more use cases to make sure the language allows all kinds of hardware designs, and we will add new constructs if necessary.